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DEMO - Learn VHDL and FPGA Development
DEMO - Learn VHDL and FPGA DevelopmentComputer Software Engineering Tools Courses |
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| Superadmin | 06.06.18 | 354 | No Rating | |
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| Learn how to create a VHDL design that can be simulated and implemented on an FPGA development board. VHDL and FPGA Development for Beginners and Intermediates is a course that is designed to teach students how to create and successfully simulate their VHDL design. We will also be implementing these designs on a Xilinx BASYS 2 FPGA development board so that the students can see their designs actually running. This course starts from beginning to end in teaching the user how to turn their digital logic design into VHDL designs that can be simulated in ModelSim or ISim and then implemented on an FPGA development board. This course also covers how to use Altera's tools so students are not limited to Xilinx development boards. Course Structure: This course contains over 20 lectures that will teach students the syntax and structure of VHDL. The student will be able to understand the syntax and use of specific VHDL keywords by taking this course. There are lectures included in each lab to give a background on the digital logic circuit the student will be implementing. This course contains 7 labs that are designed so that the student will learn how to develop VHDL code. For each lab I will give the student a set of VHDL files that they will have to modify or change in order to get the project to simulate correctly in ModelSim and so they can implement the design on their FPGA board. These labs are design to help the students learn VHDL by actually coding it themselves. Please message me before you sign up for this course! What are the requirements? Purchase a Basys 2 FPGA Development board Download Xilinx ISE webpack, but we will cover that in this course! Basic understanding of Binary Notation Basic understanding of Hexadecimal Notation Basic understanding of Logic Gates What am I going to get from this course? Over 47 lectures and 5.5 hours of content! Intro to VHDL and FPGA development Understand the design process for implementing a digital design onto a FPGA Learn how to simulate a design in Altera’s ModelSim and Xilinx Isim Learn how to use Xilinx ISE tool to program FPGA Debug a VHDL design using ModelSim Simulate a VHDL design using ModelSim Familiarize yourself with Altera and Xilinx tools Program a FPGA What is the target audience? Engineering Students Engineering Managers Digital Logic Enthusists Individuals pursuing Electrical Engineering Anyone who wants to take it for fun Section 1: Contact Information Lecture 1 Contact Information 1 page Section 2: BASYS 2 Board Lecture 2 BASYS 2 Board 01:48 Lecture 3 BASYS 2 Board Overview 05:33 Section 3: Introduction Lecture 4 Introduction to VHDL 13:46 Section 4: VHDL Language Basics Lecture 5 Data Types 20:02 Lecture 6 Syntax 08:38 Quiz 1 1 VHDL Basics 5 questions Section 5: VHDL Coding Structure Lecture 7 VHDL Design Structure 04:32 Lecture 8 VHDL Coding Styles 04:08 Lecture 9 VHDL Test Benches 08:10 Quiz 2 VHDL Coding Structure10 questions Section 6: Altera Tools Lecture 10 Altera Tools Introduction 02:11 Lecture 11 ModelSim VHDL Simulation Tool 05:32 Lecture 12 Quartus II FPGA Development Tool 04:00 Quiz 3 Altera Tools 10 questions Section 7: Xilinx Tools Lecture 13 Xilinx Tools Introduction 01:09 Lecture 14 ISim VHDL Simulation Tool 02:13 Lecture 15 Xilinx ISE FPGA Development Tool 07:44 Lecture 16 Programming The BASYS 2 FPGA Development Board 01:38 Quiz 4 Xilinx Tools10 questions Section 8: Lab 1 - Full Adder Lecture 17 Introduction 02:08 Lecture 18 Demonstration 01:37 Lecture 19 Solution 14:05 Section 9: Lab 2 - Shift Register Lecture 20 Introduction 02:17 Lecture 21 Demonstration 03:18 Section 10: Lab 3 - Universal Shift Register Lecture 22 Introduction 01:48 Lecture 23 Demonstration 05:53 Lecture 24 Solution 21:50 Section 11: Lab 4 - 7 Segment Display Lecture 25 Introduction 02:25 Lecture 26 Demonstration 04:20 Section 12: Lab 5 - Counter Lecture 27 Introduction 01:24 Lecture 28 Demonstration 02:39 Section 13: Lab 6 - Multiplier Lecture 29 Introduction 03:03 Lecture 30 Demonstration 04:46 Section 14: Lab 7 RC Servo Lecture 31 Introduction 12:43 Lecture 32 Demonstration 04:01 Section 15: Feedback Lecture 33 Survey 1 page Section 16: Lecture Notes Lecture 34 Introduction to VHDL Notes 14 pages Lecture 35 Data Types Notes 20 pages Lecture 36 Syntax Notes 15 pages Lecture 37 Structure Notes 9 pages Lecture 38 Coding Styles Notes 10 pages Lecture 39 Test Benches Notes13 pages Lecture 40 Altera Tools Notes6 pages Lecture 41 ModelSim Notes 16 pages Lecture 42 Quartus II Notes 12 pages Lecture 43 Xilinx Tools Notes 4 pages Lecture 44 Isim Notes 10 pages Lecture 45 Xilinx ISE Project Notes 17 pages Lecture 46 Programming BASYS Board 5 pages Lecture 47 BASYS 2 Board Notes 6 pages | ||||
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