Users Online
· Guests Online: 79
· Members Online: 0
· Total Members: 188
· Newest Member: meenachowdary055
· Members Online: 0
· Total Members: 188
· Newest Member: meenachowdary055
Forum Threads
Newest Threads
No Threads created
Hottest Threads
No Threads created
Latest Articles
DEMO - Learn VHDL Design for use in FPGA and ASIC Digital Systems
DEMO - Learn VHDL Design for use in FPGA and ASIC Digital SystemsComputer Software Engineering Tools Courses |
| Categories | Most Recent | Top Rated | Popular Courses |
 | Uploader | Date Added | Views | Rating |
| Superadmin | 01.01.70 | 407 | No Rating | |
| Description | ||||
| VHDL Design and Modeling Tutorial for both the beginner and experienced Programmer using a Xilinx FPGA Development Board Teach yourself the analysis and synthesis of digital systems using VHDL to design and simulate FPGA and ASIC digital systems. Participants learn the fundamental concepts of VHDL and practical design techniques using a Xilinx FPGA Development Board and ModelSim simulation software for hands-on experience. The VHDL methodology and design flow for logic synthesis addresses design issues related to component modeling, data flow description in VHDL and behavioral description of hardware. An emphasis is placed on understanding the hardware description language, VHDL design techniques for logic synthesis, design criteria, and VHDL applications. At the end of this course, participants will be able to accomplish the following: Describe and explain VHDL syntax and semantics Create synthesizable designs using VHDL Use Xilinx FPGA development board for hand-on experience Use the Xilinx ISE toolset Use ModelSim simulation software Design simple and practical test-benches in VHDL Design and develop VHDL models Prerequisites: Familiarity with digital logic design, electrical engineering, or equivalent experience. Even if you're now already familiar with VHDL but you've: Never used an attribute other than ‘event? Never used variables? Always used a process where a single concurrent statement would have sufficed? Never used assert or report statements except (maybe) in a test-bench? Never used an unconstrained vector or array? Never used a passive process inside of an entity? Never used a real or the math_real library package in synthesizable code? Always used a single process per signal assignment? then this course will definitely have something for you as well. You will learn finite state machine design, the two-process design methodology, test-bench design, combinatorial and sequential logic, and extensible synthesizable designs that are reusable. What are the requirements? Familiarity with digital logic design, electrical engineering, or equivalent experience What am I going to get from this course? Over 11 lectures and 3.5 hours of content! Describe and explain VHDL syntax and semantics Create synthesizable designs using VHDL Use Xilinx FPGA development board for hand-on experience Design simple and practical test benches in VHDL Use the Xilinx ISE toolset Design and develop VHDL models Use ModelSim simulation software What is the target audience? Engineers Hobbyists Makers Engineering Students Engineering Managers Section 1: Basics Lecture 1 Session 1 Preview 24:46 Quiz 1 Quiz 1 10 questions Section 2: Data types & operations Lecture 2 Session 2 Preview 33:42 Quiz 2 Quiz 2 10 questions Lecture 3 Software Tool Installation 15:48 Section 3: Concurrent statements Lecture 4 Session 3 21:47 Quiz 3 Quiz 3 10 questions Section 4: Sequential statements Lecture 5 Session 4 23:58 Quiz 4 Quiz 4 10 questions Section 5: Processes Lecture 6 Session 5 37:42 Quiz 5 Quiz 5 10 questions Section 6: Subprograms Lecture 7 Session 6 22:48 Quiz 6 Quiz 6 10 questions Section 7: Packages Lecture 8 Session 7 10:14 Quiz 7 Quiz 7 10 questions Section 8: Design for synthesis Lecture 9 Section 8 10:35 Quiz 8 Quiz 8 10 questions Section 9: Advanced topics Lecture 10 Section 9 14:43 Quiz 9 Quiz 9 10 questions Section 10: Additional libraries Lecture 11 Section 10 07:16 Read: Additional libraries Quiz 10 Quiz 10 5 questions | ||||
Ratings
Comments
No Comments have been Posted.
Post Comment
Please Login to Post a Comment.