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DEMO - VLSI CAD: Logic to Layout
DEMO - VLSI CAD: Logic to LayoutComputer Software Engineering Tools Courses |
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| About this course: A modern VLSI chip has a zillion parts -- logic, control, memory, interconnect, etc. How do we design these complex chips? Answer: CAD software tools. Learn how to build thesA modern VLSI chip is a remarkably complex beast: billions of transistors, millions of logic gates deployed for computation and control, big blocks of memory, embedded blocks of pre-designed functions designed by third parties (called “intellectual property” or IP blocks). How do people manage to design these complicated chips? Answer: a sequence of computer aided design (CAD) tools takes an abstract description of the chip, and refines it step-wise to a final design. This class focuses on the major design tools used in the creation of an Application Specific Integrated Circuit (ASIC) or System on Chip (SoC) design. Our focus in this first part of the course is on key Boolean logic representations that make it possible to synthesize, and to verify, the gate-level logic in these designs. This is the first step of the design chain, as we move from logic to layout. Our goal is for students to understand how the tools themselves work, at the level of their fundamental algorithms and data structures. Topics covered will include: Computational Boolean algebra, logic verification, and logic synthesis (2-level and multi-level). Recommended Background Programming experience (C, C++, Java, Python, etc.) and basic knowledge of data structures and algorithms (especially recursive algorithms). An understanding of basic digital design: Boolean algebra, Kmaps, gates and flip flops, finite state machine design. Linear algebra and calculus at the level of a junior or senior in engineering. Exposure to basic VLSI at an undergraduate level is nice -- but it’s not necessary. We will keep the course self-contained, but students with some VLSI will be able to skip some background material.e tools in this class. Who is this class for: You should be taking this course if (1) you are interested in building VLSI design tools; (2) you are interested in designing VLSI chips, and you want to know why the tools do what they do; (3) you just like cool algorithms, that work on big cool problems that involve bits, and gates, and geometry, and graphs, and matrices, and time, etc. Syllabus Part 1 : Logic WEEK 1 Orientation In this module you will become familiar with the course and our learning environment. The orientation will also help you obtain the technical skills required for the course. 1 video, 2 readings, 1 practice quiz Video: Welcome and Introduction Reading: Syllabus Practice Quiz: Demographics Survey Reading: Tools For This Course Ungraded Programming: KBDD Ungraded Programming: MiniSat Ungraded Programming: Espresso Ungraded Programming: SIS Show less Computational Boolean Algebra In this module, we will introduce advanced Boolean algebra math concepts that make it possible to take a "computational" approach to Boolean algebra. 6 videos, 2 readings Reading: Week 1 Overview Video: Computational Boolean Algebra: Basics Video: Computational Boolean Algebra: Boolean Difference Video: Computational Boolean Algebra: Quantification Operators Video: Computational Boolean Algebra: Application to Logic Network Repair Video: Computational Boolean Algebra: Recursive Tautology Video: Computational Boolean Algebra: Recursive Tautology—URP Implementation Reading: Week 1 Assignments Show less WEEK 2 Boolean Representation via BDDs and SAT Week 2 introduces two powerful and important representation techniques that allow us to do SERIOUS computational Boolean algebra, on industrial-scale designs. 7 videos, 2 readings Reading: Week 2 Overview Video: BDD Basics, Part 1 Video: BDD Basics, Part 2 Video: BDD Sharing Video: BDD Ordering Video: Satisfiability (SAT), Part 1 Video: Boolean Constraint Propagation (BCP) for SAT Video: Using SAT for Logic Reading: Week 2 Assignments Show less Graded: Problem Set #1 Graded: Programming Assignment #1: Unate Recursive Complement WEEK 3 2-Level Logic Synthesis, and Multi-Level Logic Synthesis via the Algebraic Model In Week 3, we will move from "representing" things to "synthesizing" things. In this case, synthesis means "optimization", or maybe the word "minimization" is more familiar from hand work with Kmaps or Boolean algebra. 8 videos, 2 readings Reading: Week 3 Overview Video: 2-Level Logic: Basics Video: 2-Level Logic: The Reduce-Expand-Irredundant Optimization Loop Video: 2-Level Logic: Details for One Step: Expand Video: Multilevel Logic and the Boolean Network Model Video: Multilevel Logic: Algebraic Model for Factoring Video: Multilevel Logic: Algebraic Division Video: Multilevel Logic: Role of Kernels and Co-Kernels in Factoring Video: Multilevel Logic: Finding the Kernels Reading: Week 3 Assignments Show less Graded: Problem Set #2 WEEK 4 Multilevel Factor Extract and Don't Cares You now know that to factor a multi-level network to reduce its complexity, you must look at the kernels and co-kernels. You know how to "get" these for any node. But -- what do you do with a big network to actually FIND the right common divisors? This is called EXTRACTION. We then look at a new opportunity to optimize multi-level logic: Don't Cares. In simple designs, we usually regard Don't Cares as "impossible inputs" -- things that just do not happen, so we can choose the value the hardware creates to minimize the logic. More 8 videos, 2 readings Reading: Week 4 Overview Video: Mulitlevel Logic and Divisor Extraction—Single Cube Case Video: Mulitlevel Logic and Divisor Extraction—Multiple Cube Case Video: Multilevel Logic and Divisor Extraction—Finding Prime Rectangles & Summary Video: Multilevel Logic—Implicit Don't Cares, Part 1 Video: Multilevel Logic—Implicit Don't Cares, Part 2 Video: Multilevel Logic—Satisfiability Don't Cares Video: Multilevel Logic—Controllability Don't Cares Video: Multilevel Logic—Observability Don't Cares Reading: Week 4 Assignments Show less Graded: Problem Set #3 Graded: Programming Assignment #2: Serious BDDs Graded: Auxiliary Quiz of Serious BDDs WEEK 5 Final Exam There is no new content this week. Instead, you should focus on finishing the last problem set and completing the Final Exam. 1 practice quiz Practice Quiz: End of Course Survey Show less Graded: Problem Set #4 Graded: Final Exam Part II - Layout WEEK 1 Orientation In this module you will become familiar with the course and our learning environment. The orientation will also help you obtain the technical skills required for the course. 2 videos, 2 readings, 1 practice quiz Video: Welcome and Introduction Reading: Syllabus Practice Quiz: Demographics Survey Reading: Tools For This Course Video: Two Tools Tutorial Show less ASIC Placement In this second part of our course, we will talk about geometry. We will begin with an overview of the ASIC layout process, and discuss the role of technology libraries, tech mapping (a topic we delay until the following week, to let those who want to do the Placer programming assignment have more time), and placement and routing. In this set of lectures, we focus on the placement process itself: you have a million gates from the result of synthesis and map, so, where do they go? This process is called “placement”, and we describe an iterative method, and a mathematical optimization method, that can each do very large placement tasks. More 9 videos, 2 readings Reading: Week 1 Overview Video: Basics Video: Wirelength Estimation Video: Simple Iterative Improvement Placement Video: Iterative Improvement with Hill Climbing Video: Simulated Annealing Placement Video: Analytical Placement: Quadratic Wirelength Model Video: Analytical Placement: Quadratic Placement Video: Analytical Placement: Recursive Partitioning Video: Analytical Placement: Recursive Partitioning Example Reading: Week 1 Assignments Show less WEEK 2 Technology Mapping Technology Mapping! We omitted one critical step between logic and layout, the process of translating the output of synthesis -- which is NOT real gates in your technology library -- into real logic gates. The Tech Mapper performs this important step, and it is a surprisingly elegant algorithm involving recursive covering of a tree. Another place where knowing some practical computer science comes to the rescue in VLSI CAD. More 6 videos, 2 readings Reading: Week 2 Overview Video: Technology Mapping Basics Video: Technology Mapping as Tree Covering Video: Technology Mapping—Tree-ifying the Netlist Video: Technology Mapping—Recursive Matching Video: Technology Mapping—Minimum Cost Covering Video: Technology Mapping—Detailed Covering Example Reading: Week 2 Assignments Show less Graded: Problem Set #1 Graded: Programming Assignment #3: Placer WEEK 3 ASIC Routing Routing! You put a few million gates on the surface of the chip in some sensible way. What's next? Create the wires to connect them. We focus on Maze Routing, which is a classical and powerful technique with the virtue that one can "add" much sophisticated functionality on top of a rather simple core algorithm. This is also the topic for final (optional) programming assignment. Yes, if you choose, you get to route pieces of the industrial benchmarks we had you place in the placer software assignment. More 9 videos, 2 readings Reading: Week 3 Overview Video: Routing Basics Video: Maze Routing: 2-Point Nets in 1 Layer Video: Maze Routing: Multi-Point Nets Video: Maze Routing: Multi-Layer Routing Video: Maze Routing: Non-Uniform Grid Costs Video: Implementation Mechanics: How Expansion Works Video: Implementation Mechanics: Data Structures & Constraints Video: Implementation Mechanics: Depth First Search Video: From Detailed Routing to Global Routing Reading: Week 3 Assignments Show less Graded: Problem Set #2 WEEK 4 Timing Analysis You synthesized it. You mapped it. You placed it. You routed it. Now what? HOW FAST DOES IT GO? Oh, we need some new models, to talk about how TIMING works. Delay through logic gates and big networks of gates. New numbers to understand: ATs, RATs, SLACKS, etc. And some electrical details (minimal) to figure out how delays happen through the physical geometry of physical routed wires. All together this is the stuff of Static Timing Analysis (STA), which is a huge and important final "sign off" step in real ASIC design. More 8 videos, 2 readings Reading: Week 4 Overview Video: Basics Video: Logic-Level Timing: Basic Assumptions & Models Video: Logic-Level Timing: STA Delay Graph, ATs, RATs, and Slacks Video: Logic-Level Timing: A Detailed Example and the Role of Slack Video: Logic-Level Timing: Computing ATs, RATs, Slacks, and Worst Paths Video: Interconnect Timing: Electrical Models of Wire Delay Video: Interconnect Timing: The Elmore Delay Model Video: Interconnect Timing: Elmore Delay Examples Reading: Week 4 Assignments Show less Graded: Problem Set #3 Graded: Programming Assignment #4: Router WEEK 5 Final Exam There is no new content this week. Instead, you should focus on finishing the last problem set and completing the Final Exam. 1 practice quiz Practice Quiz: End of Course Survey Show less Graded: Problem Set #4 Graded: Final Exam | ||||
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